An Automatic Design and Implementation Framework for Reconfigurable Logic IP Core

Conventional full-custom reconfigurable logic device design and implementation are time consuming processes. In this research, we propose a design framework in order to improve FPGA IP core design efficiency by link academic FPGA design flow and commercial VLSI CADs based on the synthesizable method. A novel FPGA routing tool is developed in this framework, namely the EasyRouter. By using simple templates, EasyRouter can automatically generate the HDL codes and the configuration bitstream for an FPGA. With this design flow, accurate physical information can be reported when a new FPGA architecture is evaluated with reliable commercial VLSI CADs. For FPGA architectures that cannot be easily implemented with present VLSI process, EasyRouter provides a fast performance analysis flow, which improved delay accuracy 5.1 times than VPR